As ASIC technology progresses, it is becoming possible to embed large, standard macrofunctional units within an ASIC chip, surrounded by user-specific logic. An appropriate example of such an embedded macrofunctional unit is a microprocessor.
A standard microprocessor usually has a set of test vectors that can be used to test it in a stand alone mode. The test vectors are generally applied to the microprocessor inputs, and the microprocessor outputs are monitored for predicted response. However, as the microprocessor becomes embedded within additional customer-specific logic, the inputs and outputs (I/O) become "buried", and the test parameters become less and less valid, significantly complicating or preventing the use of stand-alone test vectors. While new test regimens (sets of test vectors) can be generated which account for the influence oft he additional user or application specific logic surrounding the embedded microprocessor, such an approach would require a new or modified test regimen for each instance of an embedded microprocessor, on a case-by-case basis. This would result in additional development costs for the chip.
What is needed is a technique for isolating the microprocessor, so that standard test regimens can be applied to it, irrespective of surrounding logic.